Nowadays, electronic devices are developed to provide increased functionality. Single chips with multiple integrated functions are therefore required to have extended functionality and be able to fit into small electronic devices. To integrate more functions in a single package, the package structure of the chip has evolved from a two-dimensions to three-dimensions and from a single-die package structure to a multiple-die package structure.
A chip-stacked package structure is a semiconductor package structure with several chips of various functions integrated in a single package structure, wherein these chips are stacked on a substrate with surface mount technology (SMT), so as to reduce the processing steps for forming a semi conductor package and to decrease the size of the electronic device. Whereby the chip-stacked package structure has the advantages of small size, high operating frequency, high speed and low costs.
FIG. 1 illustrates a cross sectional view of a conventional chip stacked package structure 100. The chip-stacked package structure 100 comprises a substrate 110, a first chip 120, a second chip 130 and a plurality of bonding wires, such as bonding wires 140 and 150. The bonding wire 140 electrically connects the first chip 120 set on the substrate 110 to the substrate 110, and the bonding wire 150 electrically connects the second chip 130 stacked on the first chip 120 to the substrate 110.
To accommodate the arrangement of the bonding wire (the bonding wire 140) connected to the lower chip (the first chip 120); the size of the upper chip (the second chip 130 stacked on the first chip 120) must be smaller than that of the lower chip in a conventional design. Thus the design flexibility and the number of chips stacked in one single package are limited. Furthermore, it is necessary to extend the bonding wires in connecting the chips of small size with the substrate, whereby the radian of the bonding wires may be increased. Consequently, when a subsequent stamping process is conducted, the bonding wires may be wrenched off so as to make the electrical connection short and to decrease its manufacture yield.
To resolve the aforementioned problems, an alternative conventional chip-stacked package structure is provided. FIG. 2 illustrates a cross view cross-section view of an alternative conventional chip stacked structure 200. The chip-stacked package structure 200 comprises a substrate 210, a first chip 220, a second chip 230, a plurality of bonding wires, such as bonding wires 240 and 250, and a dummy chip 260 set between the first chip 520 and the second chip 230. The first chip 220 set on the substrate 210 has a bonding pad 270 electrically connected to the substrate 210 by the bonding wire 240, and the dummy chip 260 is stacked on the first chip 220. The second chip 230 is stacked on the dummy chip 260. The bonding wire 250 electrically connects the dummy chip 260 has a bonding pad 280 to the substrate 210. Since the size of the dummy chip is smaller than the size of the first chip 220 and the second chip 230, enough wiring space is provided between the lower chip (the first chip 220) and the upper chip (the second chip 230) for the bonding wire 540 electrically bonded on the lower chip. Accordingly, in this case the size of the upper chip (the second chip 230) is not limited anymore.
However, using the dummy can increase the thickness of the pancake structure and may conflict with the trend of package size minimization. Therefore, it is desirable to provide an advanced chip-stacked package structure designed to improving the processing yield so as to decrease the manufacture cost.